back to home page - back to HDL index
Welcome to VHSIC Hardware Discription Launguage (VHDL) index

Part-1 basic introduction to VHDL, Simulation and Synthesis tools and basic topics. Generic Introduction to the topic (VHDL, FPGA) 1.1   - Initial Example, Basic VHDL compilation unit, Compile and Simulate Behaive 1.2   - Logical Gates and Operations in architecture. 1.3   - Internal signals and bit_vector 1.4   - Synthesis introduction and example 1.5   - Introduction numeric data type and thier synthesis 1.6   - Introduction to package in VHDL and IEEE std_logic data type 1.7   - std_logic_vector with arithmetic operations. 1.8   - Introduction to process and variables in VHDL 1.9   - Conditional statments in process (if\elsif\else) 1.10 - Conditional statments in architecture. 1.11 - Four Examples of Mux 16->1 using process and without. Part-2 Introduction to Basic Synchronic Design Basic Concepts of Synchronic Design, practice more capability 2.1 - Initial Example of Sync Design ( intro to sync design 1) 2.2- Sync Counter with sync reset ( intro to sync design 2) 2.3 - Adding sync count enable ( intro to sync design 3) 2.4 - Counter that can chage direction( intro to sync design 4) 2.5 - Example of shift register with sync reset Part-3 Introduction Structual H\W description, H\W duplications in process and architecture Creation of H\W by connecting it from components 3.1 - connecting H\W using components 3.2 - duplication of H\W in architecture with component 3.3 - duplication of H\W using loop in process Part-4 Introduction of Arrays and Memory Devices, practice of previus topics Examples of Arrays and Memory 4.1 - Example of array of std_logic_vector with ROM 2x4 4.2 - Example 4K BYTE with mixed initialization, Building 16K BYTE ROM from 4 4K BYTE

Part-5 Writing generic HDL, combination of previus topics, Test Bench Introduction Generics HDL, complex logic Example and its Simulation 5.1 - generic sizes, and usage as components. 5.2 - General Purpose Counter-Register combinated Example. 5.3 - Simple Test Bench for simple Logic Design Example 5.4 - using process benifits for better testing (MISC loops) Part-6 Introduction to State Machine State Machine 6.1 - generic sizes, and usage as components. 6.2 - General Purpose Counter-Register combinated Example. Part-7 Advanced Test bench with ATPG - Pattern Like Simulations VHDL records for hetrogen arrays and Pattern Like process (using multi dimential arrays ) 7.1 - VHDL record as composite data type 7.2 - record\multi-array test pattern for State Machine