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VHDL - 4.2 - Example 4K BYTE with mixed initialization, Building 16K BYTE ROM from 4 4K BYTE

4 K BYTE ROM and MISC initializations ROMs can be done with larger arrays, and can be initizlized in seperate ways. in the below example we have ROM of 4K BYTE size , it wide is 1 BYTE (8 bits) and it lenght is 4K (it have 4K address). we will use positional assignemt in the constant of the array size ways to assign values ● num1(address) to num2(address) - assign same values to range of address ● num1(address) | num2(address) - assign same values to list of address (like or) ● num1(address) - assign one value to one address ● others => (values) - assign default value to rest of th e address

Example of the 4K BYTE ROM

Waveform of 4K BYTE ROM The ROM itself is very basic and simple and we we can simulate it from modelsim console directly.

Waveform of 4K BYTE ROM

Synthesis of 4K BYTE ROM overview

Synthesis of 4K BYTE ROM we will use EP4CE6E22C6 Cyclone 4 FPGA to demostrate synthesis of the 4KB ROM also what interesting the Quartos didnt use any Memory Elements but it used LUTs instead, this can happen since the memory still very small and for optimization purpose Synthesis SW will decide to use logic elemetns (LOGIC_CELLs) instead of memory bits.

Example of RTL view Below are the way how Quartos arrange LUTs

Building 16K ROM from 4 Devices of 4K ROM we can create bigger memery from smaller memory blocks, for this exaple we will take the 4KB ROM we created and from it we will make bigger ROM of 16K BYTE, the idia is to make the ROM 4K as component and then instantiate 4 of his size and link the address properly, to do the logic of address linking we use if\elsif\else statment in the process. we defined component of ROM 4K that we used ealier and then we duplicate it four times using generate statment in the architecture to achive this we used array that can hold the data of all 4 internal ROMs, and we defined this data based on address range (we control this in the process) because address of the 16K have more range the the address of the 4K ROM we used it devide it in 4 range in watch range we took data from relevant 4K ROM, and also to control the 4K ROM address properly (16K address integer is bigger then 4K can store) we used to devide its size from the range. to make the size seperation more elegantly we used SIZE_4K constant that hold size of 4K that way we not calculate eatch time size of the memory block from what we build our bigger memory but use it like block and filling the range of address.

Example of the 4K BYTE ROM

Waveform of 4K BYTE ROM we used TCL script to simulare the ROM locations, note that we have an array that store the datam however they are equal as when we instantiate the 4K ROM we used the same one. we can as well tha values i the wave form are repeating we the address we chouse load are located as same address if you observe the 4K ROM itself.

Waveform of 4K BYTE ROM

Synthesis of 16KB ROM overview

Synthesis of 16K BYTE ROM first note that we used same VHD file that constain both entity of the 4K ROM and 16K ROM and we connected them as component. in that case we need to select top level entity in the Quartos SW. we will use EP4CE6E22C6 Cyclone 4 FPGA to demostrate synthesis of the 4KB ROM hoever what we can see is that the size of logic Elements in post synthesis didnt change! same 42 LUT like in previus example of 4K, this is simpley because our ROM is fully 4K parts are identical and the top 2 bits dont affect anything at all. this caused QUARTOS to skip the logic. what more intresting is that Quatos identify this in during synthesis.

Example of RTL view (will looks somehow simmilar as 4K ROM) Below are the way how Quartos arrange LUTs (will looks somehow simmilar as 4K ROM) Note the unused pin ADDRESS 12/13