writted in VHDL compiled with Modelsim - adding count enable
- we have async reset before the main sync condition (rising_edge(clk))
- we wrep the counting DOUT_INT <= DOUT_INT + 1; with if that will check
if COUNT_ENA is '1' if it not it will not count
1. open modelsim and ensure you are in the directory where counter1.vhd is
2. write vlib work (if already did you can skip, if u not skip command will not do anything)
3. to compile write vcom counter3
then you will see that modelsim will load your VHDL file and compile it , modelsim will store in work folder
data that is relevant to the compilation
1. write vsim %nameOfEntity% (no .vhd extention)
2. to see the waveforms write add wave * the * mean that it will add all the ports\inputs.
3. force CLK 0 , 1 50 ns -r 100 ns it will make the clock signal (repeated)
4. force RST_N 0 , 1 100 ns will put RST_N to 0 for 100 ns then to '1'.
5. force RST 0
6. force COUNT_ENA 1 - if 0 will not count
7. run 1000 ns will run for 1000 ns
8. force COUNT_ENA 0 set sync count enable to 1
9. run 300 ns let it run for 3 cycle to see that no count happen.
10. force COUNT_ENA 1 set sync count enable to 0
11. run 1000 ns continue count again.
at this point the simulation became long and it preffered to use modelsim script (based on TCK\TK)
we can see that when COUNT_ENA is 0 counter stop count.
