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VHDL - Conditional statments in architecture.

Conditional Statments in architecture
we can performe some simple conditional statments and decition directly in architecture, in some case it might be preffer over using a process, for small cases for decition we would use when statment.

syntax
signal\output <= value when boolean condition else value2;

full Example from right.
Example of simple conditional assignment

Waveform of 2 bit comperator
Below are 2-bit comperator with compare 2 bit inputs, and have 2 outputs, one to define if A > B or not. and the second to define if they equal.

Simulation done with TCL script that tests the desired behaves A > B, A < B, A = B.

we can see the waveform behaive as expected..


Note that system behaive same like this.
Waveform of ...