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VHDL - Conditional statments in process (if\elsif\else)

Conditional Statments in Process
Process allows to use conditional statments, which improve its capability significantly, and make it act simmilar to programming launguage - this is extreamly usefull to describe complex alghoritms

we can use if-elsif-case statments in process which can make decition making much simple and more intuitive

Basic form of statment
if boolean_tested_value then
     sequantial statments
elsif another_boolean_tested_value then
     sequantial statments
else
     sequantial statments
end if;

Key notes about using process - reminder

1. all inputes that used in process MUST be appear in sensitivety list!

2. when creating Logic systems that are planned to pass synthesis DO NOT USE wait statment.

3. statments in process Executed sequantially.

4. variables DO NOT LIVE outside the process. (Excepions will be discussed later..)

5. conditional statments (if,elsif,switch) statments dont live outside the process.


in the below example we created simple comperator for 2 bit inputs using if\elsif\else statnents and with using arithmetic operations (relations) on std_logic_vector.
Example of simple conditional assignment

Waveform of 2 bit comperator
Below are 2-bit comperator with compare 2 bit inputs, and have 2 outputs, one to define if A > B or not. and the second to define if they equal.

Simulation done with TCL script that tests the desired behaves A > B, A < B, A = B.

we can see the waveform behaive as expected..


Note that system behaive same like this.
Waveform of ...