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VHDL - Introduction to package in VHDL and IEEE std_logic data type

General Package Example Package is an Basic Compilation unit - it possible to compile Package on its own it mean that we can compile package seperatly from VHDL system aka we dont need entity first, also note that we can use package with several entitys. package can have 1. package declaration - see example in right, it used for declaration on constants and functions from left you can see an example of simple package 2. package body - used for functions and procedure (include internal functions) implementaion, this is optional part as it not mandatory to use it.	Example of very simple package
Compile Package package can be compiled sepereratly from entity and\or architecture, note that when you use the package in entity it must be compiled before	Modelsim console
How to use package 1. it must be compiled first 2. we need to include it before the entity - the most commen way is by using use work.package_name.all. 3. we can include every constant one by one like this 4. another to use package is like this average developer will preffer use this work.package_name.all. this is because it will make all the elements in package be visible	Modelsim console
Simulation of the system note that we compilled the package first and only then we compiled the vhd file with the entity that use it.
Waveform below are behaive of your system, we just masking everything bit first bit of the input signal.	Waveform of ...

Introduction to IEEE-1164 (STD Logic data type)

The IEEE 1164 Standard describe the difinition of logic values for VHDL design. it consist of 9 logic values. '0' Logic '0' ,strong drive '1' Logic '1' ,strong drive 'L' Logic '0' ,weak drive 'H' Logic '1' ,weak drive 'Z' High Impedence (Tri State) 'X' unknown state, strong drive 'W' unknown state, weak drive 'U' un-initilized value '-' Logic dont care to use the std_logic data type we need to add the IEEE library and from the library we need to use the std_logic package that conain the definitions of this data type, in names std_logic_1164. Notes 1) the IEEE-1164 support both single bit (std_logic) and bit_vector std_logic_vector similar like bit,bit_vector 2) IEEE-1164 aka std_logic and std_logic_vector are the most common data types and we will use them from now in most of the cases. 3) IEEE-1164 are supporting arithmetic operations in vectors - it will be discussed later. 4) IEEE-1164 may have issues with synthesis - this will be discussed late 5) when using the IEEE-1164 library need to write library ieee; and to use the std_logic/std_logic_vector need to write use ieee.std_logic_1164.all the reason because the std_logic_1164 package not compilled into work folder but exiting in the ieee library.

Example of usage of std_logic data type for port Below is simple 3 gate AND gate, implemented with std_logic. Modelsim simmulation (using std_logic data types) note that we combine the speciel std_logic data types, also see that '0' and anyvalue is '0'