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VHDL - 4.1 - Example of array of std_logic_vector with ROM 2x4

arrays in VHDL we can define arrays from multiple data types, need to notice that bit_vector\std_logic_vector are arrays from bit\std_logic. array in VHDL can be constrained and un-constrained Example1: type myArrayOfBits is array (0 to 7) of bit; Example2: type std_logic_vector is array (natural range <> of std_logic; The second example is from standard std_logic_1164 package. Example of Simple ROM 2 x 4 in this SImple Example we will a have a simple ROM memory that have 2 adress and 4 bit wide of memory, we used the address as ineteger as VHDL does not translate index (integer) to std_logic, when we cover functions we will solve this more elegantly, however the integer data type fully supported by synthesis S\W.

Example of the ROM 2 x 4

Waveform of ROM 2 x 4 The ROM itself is very basic and simple and we we can simulate it from modelsim console directly.

Waveform of ROM 2 x 4

Synthesis of ROM 2 x 4 overview

Synthesis of ROM 2 x 4 Gate we will use EP4CE6E22C6 Cyclone 4 FPGA to demostrate synthesis of the ROM 2 x 4 also what interesting the Quartos didnt use any Memory Elements and even didnt use LUTs (Logic Cells) at all. the reason is because of ROM is extreamly simple, the Synthesis S\W were able to represent it with simpele line with 2 NOTs on the way.

Example of RTL view Below are the way how Quartos arrange LUTs