in architecture all the statments are beeing executed concurently (aka in same time), and each of the statments can be considered like a process that eatch of them (what in the architecture) are beeing executed as same time, however it possibe to define the process and include commands in to it which will be simmilar to programming lauguage and this canh increase the VHDL capability.
process form
process(sensitivety list( signals\inputs) )
MISC declarations like variables
begin
sequantial statments
end process
Notes
1. process can be in 2 states it can be active (trigger by change in signal of sensitivety list) or suspended.
2. it possible to use intead of sensetivety list wait on statment on signals that used to tigger the process, however when writing HDL for digital systems this way of writing HDL is may not be supported by synthesis S\W and should be avoided. the wait on statments sometimes usefull for simulations.
3. all inputes that used in process MUST be appear in sensitivety list!
4. do NOT mix the sensetivety list and wait on statments in same process even for simulation.
5. process contain declaratibe part (before the begin statment) and executional part (after the begin statment, in the declarative part we usually use for variables declarations (other usages will be discussed later).
6. multiple process in architecture arc executed concurently (aka in same time)
7. process can be executed concurently with other regular statments in the architecture like logic operations, (the logic operation line like y <= a and b are considered as process of its own).
8. IMPORTANT assignments to signals in process happen in same time after process executed, it important to use variables when try to assign inside a process.
Below the waveform for simulation of that process
1. Example of mix of process and other assigments in architecture
waveform of the PROCESS3 example
2.Example of wait on statments intead of sensetivety list
waveform of the PROCESS2 example
RTL view
looks like synthesis S\W not like it
