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VHDL - Synthesis introduction and Example

Synthesis in general Synthesis or "Logic Synthesis" when high level H\W discription ( usually RTL) are translated to low level implementation of Logic Gates. some synthesis S\W are targeted for Programmable Devices such as FPGA, CPLD, PAL etc. while other are used for ASICs. Register-Transfer-level (RTL) - RTL used to create high level high level represendation of a circuit, most commen RTL represendation is a Synchronous circuit (or Synchronous design) which consist of 2 elements. 1. an Registers (Sequantial logic). (builded from Flip Flops - usually D Flip Flips.) 2. Combinational logic - performs the logic operations and builded from Logic Gates.

Basic Example Simple Gate - not Sync design as it dont have registers Notes 1. we cannot use a nand b nand c as nand is not associative logic operation. 2. to implement nand with 3 gates we can do it simple with and,not gates. like this : not(a and b and c). 3. nand gates are generic aka you can implement any other logic gate with several nand gates. (for xor we need 4 nand gates) this might be usefill when used old circuits that used TTL devices, as we may preffer 1 type of IC and use all its gate then solder several types when most if then not in use. 4. in modern FGPA there is no restriction or concern about logic elements quantity , anyway it preffer not to make complex code as it will make hard it to maintain, thus synthesis S\W will transte and optimize it on her own. it mean that not(a and b and c) style are preffered!	Source Code
Compile and simulate we used TCL basec script to simulate the logic. note that we didnt use "add wave *" but added every signal\port one by one, using add wave nameOfSignal\port, also we added seperator to the waveform , it can be usefill when design contain a very large amount of signals. Example of TCL Script	Modelsim Console
Waveform of the NAND3 gate below are wave form that represend behaive of the NAND3 Gate, we used add wave -divide "internal" to represend the internal signals more clearly, in large systems number of signals will be inclresed significatnly and arranging waveform tools can be usefull. only when all inputs are '1' the output will be '0', we didnt conver all the permutations as it not nessesary. also to do this (cover all testing permutations) it preffer to use Test Bench that can use loops or a Automatically generated Test Patterns.	Waveform of ...

RTL View RTL View of the system - indeed it was sythesised for more readable form Important! Synthesis S\W (Quartus) have conflict with its own component NAND3 so we change the name of the entity

Technilogy Lap View Technilogy Lap View - how it implement on the FPGA (EP4CE22E22C8)