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VHDL - 3.3 - duplication of H\W using loop in process

duplication of H\W using loop in process we can duplicate H\W in loop using process, we used loop in process that have one temporary variable for calculations purpose, we first initialized it to '1' otherwise result will stuck at '0' and then we duplicated it using for loop eachtime doing and with the input after loop dont we assign the the result to the output Y note that when we assign to variable we use the := operator. when we assign to the signal or outputs(out\inout\buffer) we use the <= operator. Additional note 1. we build it from 8 gates. instead we can do 100 or 2000 just change the index in the vectors. 2. we have onlt input (as vector) and it must appear in process sensitivity list. 3. variables are are exist inside process only. 4. for loop used to duplicate H\W in process, it also have its own variable i that not need to be declared explicitly we can use it inside the loop scope (till end loop). Alternative describe of AND with 8 gates using generate statment here.

Example of the AND_B gate

Waveform of AND with 8 inputs we used it with same exact TCL script we used to simulate the AND8 in the duplication using generate.

Waveform of AND with 8 inputs

Synthesis of AND8 Gate and the loops in process overview

Synthesis of AND8 Gate we will use EP4CE6E22C6 Cyclone 4 FPGA to demostrate synthesis of the AND8 Gate by using loops, as synthesis pass without any issue also observe that we used only 3 logic elements from the Device. we can see in the post fitting image that 3 logic elements (FPGA LUTs) we re used to create the logic for the 8 input AND gates. the LUTs named "LOGIC_CELL_COMB", the inputs and the outputs are visiable as well, also quartos identify the Intenel variable, however it does not have logic of its own. other elemets in the Technology map are internal quartos parts (they not visiable in the RTL).

Example of RTL view Below are the way how Quartos arrange LUTs